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the proposed alu design is based on the existing alu design but the logic implementation has been modified to reduce the area, power and delay. the proposed design consists of 3 basic modules. the first module is the 8 bit alu, second module is the 4 bit alu and the third module is the multiplier. this paper presents the design and the results of the proposed design.

download full-text pdf cite this publication mohanarangan s, dr. g. a sathishkumar, 2016, design and implementation of alu chip using d3l logic and ancient mathematics, international journal of engineering research & technology (ijert) ncspc 2016 (volume 4 issue 14),

download full-text pdf cite this publication mohanarangan s, dr. g. a sathishkumar, 2016, design and implementation of alu chip using d3l logic and ancient mathematics, international journal of engineering research & technology (ijert) ncspc 2016 (volume 4 issue 14),

download full-text pdf cite this publication mohanarangan s, dr. g. a sathishkumar, 2016, design and implementation of alu chip using d3l logic and ancient mathematics, international journal of engineering research & technology (ijert) ncspc 2016 (volume 4 issue 14),

download full-text pdf cite this publication mohanarangan s, dr. g. a sathishkumar, 2016, design and implementation of alu chip using d3l logic and ancient mathematics, international journal of engineering research & technology (ijert) ncspc 2016 (volume 4 issue 14),

our alu design is a processor independent design which can be implemented in any fpga product. it can be used in any design. the basic architecture of the proposed architecture is a streamlined implementation of a full 16 bit binary arithmetic. it can be extended to higher bit lengths as well. it makes use of the d3l logic for better performance.
using the proposed design is much less area, power and delay. it also shows a better performance in terms of speed, power and delay. hence the proposed design can be implemented in the industry as it is very easy to design and implement. further study on wide area and cost effective implementation of the proposed design in various fpga products is needed.
the proposed alu design for 16 bits multiplier and a 64-bit alu that uses d3l logic is 5 times smaller in area, 100 times smaller in delay and 0.3 watt lower in power consumption compared with the existing design. the proposed design requires 1.75 million gates compared with 19 million gates required by the existing design. the peak power usage of the proposed design is 0.97 watts while the existing design requires 10.6 watts.
the proposed alu architecture is also independent of the size of the alu. this is because for smaller alu, smaller d3l logic is used while for larger size alu, larger d3l logic is used for better performance.
the simulated results for the proposed design is also very satisfactory. the average performance of the 32-bit, 16-bit and 8-bit implementations of the proposed architecture is close to the actual design. the performance of the proposed design is found to be close to the actual design. this indicates that the proposed design is not only simpler but also more accurate in terms of timing and area. the proposed design is compared with different multiplier designs available in the market, many of them are found inefficient in terms of area and delay. in the current paper, we proposed a simple multiplier design which in the future, can be extended for higher bit lengths.
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